Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders
Article in Journal of Real-Time Image Processing (October 2017)
The most recent citing publications are shown below. View all 4 publications that cite this research output on Dimensions.
FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis
Article in Image Processing & Communications (June 2017)
ASiPEC: An Application Specific Instruction-Set Processor for High Performance Entropy Coding
Book chapter (March 2015)