Workload partitioning procedure for null message-based PDES Grant US-10929194-B2 United States of America 23 Feb 2021
Methods for bounding the number of delayed reset clock cycles for retimed circuits Application US-10354038-B1 United States of America 16 Jul 2019
Workload partitioning procedure for null message-based PDES Grant US-9798587-B2 United States of America 24 Oct 2017
IC phase detector with re-timed reference clock controlling switches Grant US-9742416-B2 United States of America 22 Aug 2017
Optimizing integrated circuit design through use of sequential timing information Grant US-8589845-B2 United States of America 19 Nov 2013
REFERENCE CLOCK RE-TIMING SCHEME IN ELECTRONIC CIRCUITS Application US-20130211758-A1 United States of America 15 Aug 2013
Boundary buffers to model register incompatibility during pre-retiming optimization Grant US-8423939-B1 United States of America 16 Apr 2013
Reducing critical cycle delay in an integrated circuit design through use of sequential… Application US-8307316-B2 United States of America 06 Nov 2012
Constraint based retiming of synchronous circuits Application US-7945880-B1 United States of America 17 May 2011
Optimization of combinational logic synthesis through clock latency scheduling Grant US-7559040-B1 United States of America 07 Jul 2009
Verification of scheduling in the presence of loops using uninterpreted symbolic… Grant US-7383166-B2 United States of America 03 Jun 2008
Verification of scheduling in the presence of loops using uninterpreted symbolic… Grant US-6745160-B1 United States of America 01 Jun 2004
Enhanced binary decision diagram-based functional simulation Grant US-5937183-A United States of America 10 Aug 1999
Test generation of sequential circuits using software transformations Grant US-5574734-A United States of America 12 Nov 1996
Method for identifying untestable and redundant faults in sequential logic circuits. Grant US-5559811-A United States of America 24 Sep 1996